CMOS VLSI Design Lab
1. (10 pts.) Inverter Create a schematic diagram for a CMOS inverter and simulate its transient
behavior for three different capacitive loads: (1) Cload = 0.01pF; (2) Cload = 0.05pF; and (3)
Cload = 0.1pF. For each load capacitance, determine (a) the rise time (tr); (b) fall time (tf) of
the output voltage; and (c) the rise and fall propagation delays (tpdr and tpdf) of the inverter.
Assume the input fall and rise time to be 0.1ns. State these measured values in your report.
2. (10 pts.) 2-input NAND Gate Create a schematic diagram for a 2-input NAND gate and using pulse
sources (PULSE) for the two inputs, verify its truth table. Assume that the NAND gate drives a
load capacitance of 0.01pF at its output.
3. (10 pts.) 2-input NOR Gate Create a schematic diagram for a 2-input NOR gate and using pulse
sources for the two inputs, verify its truth table. Assume that the NOR gate drives a load
capacitance of 0.01pF at its output.
Sample Solution
A complementary CMOS inverter is executed as the series connection of a p-device and an n-device, as shown in the Figure above. The source and the substrate (body) of the p -device is tied to the VDD rail, while the source and the substrate of the n-device are connected to the ground bus. Thus, the devices do not suffer from anybody effect. To derive the DC transfer characteristics for the CMOS inverter, which depicts the variation of the output voltage (Vout)(Vout) as a function of the input voltage (Vin)(Vin), one can identify five following regions of operation for the n -transistor and p -transistor.
