based on various factors such as capacitance, resistance or both. The non-uniformity is due to the uneven grouping of the sinks in the window based on a constraint. The buffers are placed at the nodes of the clock mesh, which are distributed based on the density of the sinks in the window. As it forms a grid structure the path sharing of the sinks to the source is more as a node is connected to every other node. Thus the buffer depth is very shallow, maybe a single stage. Hence there is very less induction of skew due to the process variations.

The clock tree consumes less power when compared to the cock mesh as there is increase in the wire length and hence total wire capacitance of the mesh which amounts for higher power consumption. But as the technology node reduces and the logic becomes denser, the skew due to the process variations becomes more predominant in clock tree rather than in clock mesh. Hence in deep sub-micron technology clock mesh is preferred.
In this work we study the following aspects of the clock mesh synthesis for deep sub micron technologies-
The formation of a non-uniform clock mesh with respect to a given target capacitance of the clock sinks inside every window of the mesh.
Connection of the clock sinks with the nearest edge of the clock mesh window using stubs and calculating the wire total length for different target capacitances.
Placement of the buffer of different sizes with respect to the total sinks capacitance in a given window.
Varying the voltage and the frequency probed to the mesh and calculating the total skew in the mesh.
The rest of the paper is sectioned as follows:-
The first section will contain the algorithm to form the non-uniform mesh and the connection of the clock sinks using stubs
The second section will contain the procedure for the placement of the buffers.

The third section will contain the study of the mesh for differential voltage and frequency.
The fourth section will contain the simulation of the mesh to obtain the skew and the power consumed