ordinatesand B3 are placed and so on.
If there were a case wherein the co-ordinates of the centroid of two mesh windows are nearest to the same mesh node then the capacitance of the two meshes are added and an equivalent buffer is referred from the table and placed.

The buffer placement does not stop after buffers are placed for all sinks. It is an iterative process as will be shown further in this paper. The buffers are further shuffled and reordered until the skew and the power requirements are reached because the wire capacitance further adds to the total capacitance and increases the power consumed. Hence the buffer placement is an NP-complete complexity class problem.
SIMULATION OF THE MESH IN NGSPICE
Once the placement of buffer is done, a netlist containing the information regarding the placement and sizes of the buffer and the capacitances they are driving is generated in MATLAB. The netlist generated is saved under the *.cir extension with the syntax shown below
[Component Name] [positive Node] [negative Node] [Value]
The mesh maybe modeled as delta connected network (??-connected) or a star connected network (??- connected network). This paper incorporates the delta-connected network of the mesh as well as the stub connection to model the netlist file.
Once the netlist is generated and saved as a *.cir format, it is imported to NGSPICE. On importing the netlist to NGSPICE, a parametric analysis is performed for different values of voltage and frequency targeting a 45nm technology.
The netlist is generated for four quadrants each of which is imported into NGSPICE successively and simulated. We calculate the latency of the clock signals inside each window of a given quadrant.
The buffers are first probed and then external clock pulses are passed through it. This means that external contacts are given to the nodes where the buffers are placed and clock input is given in the form of variable pulses. A parameterized analysis is done in three steps. Firstly we obtain the latency at the clock sinks by varying the voltage and keeping the frequency of the clock pulses constant. Next we vary the frequency of the clock pulses and keep the voltage constant. Finally we vary both the voltage and frequency of the clock pulses and obtain the latency values at the sinks.